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system diagram example frequencies: dat 48khz or cd 44.1khz or broadcast 32khz ad1890/ AD1891 output sample clock input sample clock input serial data output serial data example frequencies: dat 48khz or cd 44.1khz or broadcast 32khz rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a sampleport stereo asynchronous sample rate converters ad1890/AD1891 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features automatically sense sample frequenciesno programming required tolerant of sample clock jitter smooth transition when sample clock frequencies cross accommodate dynamically changing asynchronous sample clocks 8 khz to 56 khz sample clock frequency range 1:2 to 2:1 ratio between sample clocks C106 db thd+n at 1 khz (ad1890) 120 db dynamic range (ad1890) optimal clock tracking control Cshort/long group delay modes Cslow/fast settling modes linear phase in all modes equivalent of 4 million 22-bit fir filter coefficients stored on-chip automatic output mute flexible four wire serial interfaces low power applications digital mixing consoles and digital audio workstations cd-r, dat, dcc and md recorders multitrack digital audio and video tape recorders studio to transmitter links digital audio signal routers/switches digital audio broadcast equipment high quality d/a converters digital tape recorder varispeed applications computer communication and multimedia systems product overview the ad1890 and AD1891 sampleports? are fully digital, stereo asynchronous sample rate converters (asrcs) that solve sample rate interfacing and compatibility problems in digital audio equip- ment. conceptually, these converters interpolate the input data up to a very high internal sample rate with a time resolution of 300 ps, then decimate down to the desired output sample rate. the ad1890 is intended for 18- and 20-bit professional applications, and the AD1891 is intended for 16-bit lower cost applications where large dynamic sample-rate changes are not encountered. these devices are asynchronous because the frequency and phase relationships between the input and output sample clocks (both are inputs to the ad1890/AD1891 asrcs) are arbitrary and need not be related by a simple integer ratio. there is no need to explicitly select or program the input and output sample clock frequencies, as the ad1890/AD1891 automatically sense the relationship between sampleport and sampleports are trademarks of analog devices, inc. the two clocks. the input and output sample clock frequencies can nominally range from 8 khz to 56 khz, and the ratio between them can vary from 1:2 to 2:1. the ad1890/AD1891 use multirate digital signal processing techniques to construct an output sample stream from the input sample stream. the input word width is 4 to 20 bits for the ad1890 or 4 to 16 bits for the AD1891. shorter input words are automatically zero-filled in the lsbs. the output word width for both devices is 24 bits. the user can receive as many of the output bits as desired. internal arithmetic is performed with 22-bit coefficients and 27-bit accumulation. the digital samples are processed with unity gain. the input and output control signals allow for considerable flex- ibility for interfacing to a variety of dsp chips, aes/ebu receivers and transmitters and for i 2 s compatible devices. input and output data can be independently justified to the left/right clock edge, or delayed by one bit clock from the left/right clock edge. input and output data can also be independently justified to the word clock rising edge or delayed by one bit clock from the word clock rising edge. the bit clocks can also be indepen- dently configured for rising edge active or falling edge active operation. the ad1890/AD1891 sampleport? asrcs have on-chip digi- tal coefficients that correspond to a highly oversampled 0 khz to 20 khz low-pass filter with a flat passband, a very narrow tran- sition band, and a high degree of stopband attenuation. a subset of these filter coefficients are dynamically chosen on the basis of the filtered instantaneous ratio between the input sample clock (l r _i) and the output sample clock (l r _o), and these coeffi- cients are used in an fir convolver to perform the sample rate conversion. refer to the theory of operation section of this data sheet for a more thorough functional description. the low- pass filter has been designed so that full 20 khz bandwidth is maintained when the input and output sample clock frequencies are as low as 44.1 khz. if the output sample rate drops below the input sample rate, the bandwidth of the input signal is ( continued on page 4 )
ad1890/AD1891Cspecifications test conditions unless otherwise noted supply voltage +5.0 v ambient temperature 25 c mclk 20 mhz load capacitance 100 pf all minimums and maximums tested except as noted. performance (guaranteed over 0 c t a 70 c, v dd = 5.0 v 10%, 8 mhz mclk 20 mhz) min max units ad1890 dynamic range (20 hz to 20 khz, C60 db input)? 120 db AD1891 dynamic range (20 hz to 20 khz, C60 db input)? 96 db total harmonic distortion + noise? db ad1890 and AD1891 (20 hz to 20 khz, full-scale input, f sout /f sin between 0.5 and 2.0) C94 db ad1890 (1 khz full-scale input, f sout /f sin between 0.7 and 1.4) C106 db ad1890 (10 khz full-scale input, f sout /f sin between 0.7 and 1.4) C100 db AD1891 (1 khz full-scale input, f sout /f sin between 0.7 and 1.4) C96 db AD1891 (10 khz full-scale input, f sout /f sin between 0.7 and 1.4) C95 db interchannel phase deviation? 0 degrees input and output sample clock jitter? 10 ns (for 1 db degradation in thd+n with 10 khz full-scale input, slow-settling mode) digital inputs (guaranteed over 0 c t a 70 c, v dd = 5.0 v 10%, 8 mhz mclk 20 mhz) min max units v ih 2.2 v v il 0. 8 v i ih @ v ih = +5 v 4 m a i il @ v il = 0 v 4 m a v oh @ i oh = C4 ma 3.6 v v ol @ i ol = 4 ma 0.4 v input capacitance? 15 pf digital timing (guaranteed over 0 c t a 70 c, v dd = 5.0 v 10%, 8 mhz mclk 20 mhz) min max units t mclk mclk period 50 125 ns f mclk mclk frequency (1/t mclk ) 8 20 mhz t mpwl mclk lo pulse width 20 ns t mpwh mclk hi pulse width 20 ns f lri l r _i frequency with 20 mhz mclk? 10 70 khz t rpwl reset lo pulse width 100 ns t rs reset setup to mclk falling 15 ns t bclk bclk_i/o period? 80 ns f bclk bclk_i/o frequency (l/t bclk )? 12.5 mhz t bpwl bclk_i/o lo pulse width 40 ns t bpwh bclk_i/o hi pulse width 40 ns t wsi wclk_i setup to bclk_i 15 ns t wso wclk_o setup to bclk_o 30 ns t lrsi lr_i setup to bclk_i 15 ns t lrso lr_o setup to bclk_o 30 ns t ds data setup to bclk_i 0 ns t dh data hold from bclk_i 25 ns t dpd data propagation delay from bclk_o 40 ns t doh data output hold from bclk_o 5 ns rev. 0 C2C
ad1890/AD1891 rev. 0 C3C power (0 c t a 70 c, mclk = 16 mhz, f sin = 48 khz, f sout = 44.1 khz) min typ max units supplies voltage, v dd 2.7 5.5 v current, i dd (v dd = 5.0 v) 35 40 ma current, i dd (v dd = 3.0 v) 19 ma dissipation operation (v dd = 5.0 v) 175 200 mw operation (v dd = 3.0 v) 57 mw temperature range min max units specifications guaranteed 0 +70 c operation guaranteed C40 +85 c storage C60 +100 c absolute maximum ratings* min max units v dd to gnd C0.3 7.0 v dc input voltage C0.3 v dd + 0.3 v latch-up trigger current C1000 +1000 ma soldering +300 c 10 sec *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. digital filter characteristics? min max units passband ripple (0 to 20 khz) 0.01 db transition band 1 4. 1 khz stopband attenuation 110 db group delay (l r C i = 50 khz) 700 3000 m s ?guaranteed. not tested 1 valid only when f sout 3 f sin (i.e., upsampling), f sin = 44.1 khz. specifications subject to change without notice. ordering guide model temperature range package description package option ad1890jn 0 c to +70 c plastic dip n-28 ad1890jp 0 c to +70 c plcc p-28a AD1891jn 0 c to +70 c plastic dip n-28 AD1891jp 0 c to +70 c plcc p-28a warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1890/AD1891 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad1890/AD1891 C4C rev. 0 (continued from page 1) product overview (continued) automatically limited to avoid alias distortion on the output sig- nal. the ad1890/AD1891 dynamically alter the low-pass filter cutoff frequency smoothly and slowly, so that real-time varia- tions in the sample rate ratio are possible without degradation of the audio quality. the ad1890/AD1891 have a pin selectable slow- or fast-settling mode. this mode determines how quickly the asrcs adapt to a change in either the input sample clock frequency (f sin ) or the output sample clock frequency (f sout ). in the slow-settling mode, the control loop which computes the ratio between f sin and f sout settles in approximately 800 ms and begins to reject jitter above 3 hz. the slow-settling mode offers the best signal quality and the greatest jitter rejection. in the fast-settling mode, the control loop settles in approximately 200 ms and begins to reject jitter above 12 hz. the fast-settling mode allows rapid, real time sample rate changes to be tracked without error, at the expense of some narrow-band noise modulation products on the output signal. the ad1890 also has a pin selectable, short or long group delay mode. this pin determines the depth of the first-in, first-out (fifo) memory which buffers the input data samples before they are processed by the fir convolver. in the short mode, the group delay is approximately 700 m s. the asrc is more sensi- tive to sample rate changes in this mode (i.e., the pointers which manage the fifo are more likely to cross and become momen- tarily invalid during a sample rate step change), but the group delay is minimized. in the long mode, the group delay is ap- proximately 3 ms. the asrc is tolerant of large dynamic sample rate changes in this mode, and it should be used when the device is required to track fast sample rate changes, such as in varispeed applications. the AD1891 features the short group delay mode only. in either device, if the read and write pointers that manage the fifo cross (indicating underflow or overflow), the asrc asserts the mute output (mute_o) pin hi for 128 output clock cycles. if mute_o is connected to the mute input (mute_i) pin, as it normally should be, the serial output will be muted (i.e., all bits zero) during this transient event. the ad1890/AD1891 are fabricated in a 0.8 m m single poly, double metal cmos process and are packaged in a 0.6" wide 28-pin plastic dip and a 28-pin plcc. the ad1890/AD1891 operate from a +5 v power supply over the temperature range of 0 c to +70 c. 28 27 26 22 21 20 19 18 17 25 24 23 16 15 serial in serial out mult clock tracking accum reset lr_i lr_o 1 2 3 7 8 9 10 11 12 4 5 6 13 14 coef rom fifo gpdlys (ad1890) n/c (AD1891) mclk data_i bclk_i wclk_i v dd gnd n/c bkpol_i trglr_i msbdly_i gnd setslw gnd bclk_o wclk_o data_o v dd gnd n/c bkpol_o trglr_o msbdly_o mute_o mute_i ad1890/AD1891 n/c = no connect ad1890/AD1891 dip pinout 22 21 20 19 25 24 23 7 8 9 10 11 5 6 lr_i lr_o serial in reset serial out accum coef rom fifo mult n/c wclk_i v dd gnd bkpol_i trglr_i wclk_o data_o v dd gnd n/c bkpol_o 1 2 3 4 282726 12 13 14 18 17 16 15 gpdlys (ad1890) n/c (AD1891) mclk data_i bclk_i setlslw gnd bclk_o msbdly_i gnd trglr_o msbdly_o mute_o mute_i clock tracking ad1890/AD1891 n/c = no connect ad1890/AD1891 plcc pinout
ad1890/AD1891 rev. 0 C5C ad1890/AD1891 pin list serial input interface pin name number i/o description data_i 3 i serial input, msb first, containing two channels of 4- to 20-bits of twos-complement data per channel. AD1891 only: maximum of 16 data bits per channel; additional bits ignored. bclk_i 4 i bit clock input for input data. wclk_i 5 i word clock input for input data. this input is rising edge sensitive. (not required in l r input data clock triggered mode [trglr_i = hi].) l r _i 6 i left/ right clock input for input data. must run continuously. serial output interface pin name number i/o description data_o 23 o serial output, msb first, containing two channels of 4- to 24-bits of twos-complement data per channel. bclk_o 26 i bit clock input for output data. wclk_o 25 i word clock input for output data. this input is rising edge sensitive. (not required in l r output data clock triggered mode [trglr_o = hi].) l r _o 24 i left/ right clock input for output data. must run continuously. input control signals pin name number i/o description bkpol_i 10 i bit clock polarity. lo: normal mode. input data is sampled on rising edges of bclk_i. hi: inverted mode. input data is sampled on falling edges of bclk_i. trglr_i 11 i trigger on l r _i. hi: changes in l r _i indicate beginning 1 of valid input data. lo: rising edge of wclk_i indicates beginning of valid input data. msbdly_i 12 i msb delay. hi: input data is delayed one bclk_i after either l r _i (trglr_i = hi) or wclk_i (trglr_i = lo) indicates the beginning of valid input data. included for i 2 s data format compatibility. lo: no delay. note 1 the beginning of valid data will be delayed by one blck_i if msbdel_i is selected (hi). group delay intuitively, the time interval required for a full-level input pulse to appear at the converters output, at full level, expressed in milliseconds (ms). more precisely, the derivative of radian phase with respect to radian frequency at a given frequency. transport delay the time interval between when an impulse is applied to the converters input and when the output starts to be affected by this impulse, expressed in milliseconds (ms). transport delay is independent of frequency. definitions dynamic range the ratio of a near full-scale input signal to the integrated noise in the passband (0 to ? 20 khz), expressed in decibels (db). dy- namic range is measured with a C60 db input signal and 60 db arithmetically added to the result. total harmonic distortion + noise total harmonic distortion plus noise (thd+n) is defined as the ratio of the square root of the sum of the squares of the val- ues of the harmonics and noise to the rms value of a sinusoidal input signal. it is usually expressed in percent (%) or decibels. interchannel phase deviation difference in input sampling times between stereo channels, ex- pressed as a phase difference in degrees between 1 khz inputs.
ad1890/AD1891 C6C rev. 0 output control signals pin name number i/o description bkpol_o 19 i bit clock polarity. lo: normal mode. output data is valid on rising edges of bclk_o, changed on falling. hi: inverted mode. output data is valid on falling edges of bclk_o, changed on rising. trglr_o 18 i trigger on l r _o. hi: changes in l r _o indicate beginning 1 of valid output data. lo: rising edge of wclk_o indicates beginning of valid output data. msbdly_o 17 i msb delay. hi: output data is delayed one bclk_o after either l r _o (trglr_o = hi) or wclk_o (trglr_o = lo) indicates the beginning of valid output data. included for i 2 s data format compatibility. lo: no delay. miscellaneous pin name number i/o description gpdlys 1 i ad1890 only: group delayshort. hi: short group delay mode ( ? 700 m s). more sensitive to changes in sample rates (l r clocks). lo: long group delay mode ( ? 3 ms). more tolerant of sample rate changes. this signal may be asynchronous with respect to mclk, and dynamically changed, but is normally pulled up or pulled down on a static basis. AD1891: short group delay mode only; this pin is a n/c. mclk 2 i master clock input. nominally 16 mhz for sampling frequencies (f s , word rates) from 8 khz to 56 khz. exact frequency is not critical, and does not need to be synchronized to any other clock or possess low jitter. reset 13 i active lo reset. set hi for normal chip operation. mute_o 16 o mute output. hi indicates that data is not currently valid due to read and write fifo memory pointer overlap. lo indicates normal operation. mute_i 15 i mute input. hi mutes the serial output to zeros (midscale). normally connected to mute_o. reset lo for normal operation. setlslw 28 i settle slowly to changes in sample rates. hi: slow-settling mode ( ? 800 ms). less sensitive to sample clock jitter. lo: fast-settling mode ( ? 200 ms). some narrow-band noise modulation may result from jitter on l r clocks. this signal may be asynchronous with respect to mclk, and dynamically changed, but is normally pulled up or pulled down on a static basis. n/c 9, 20 no connect. reserved. do not connect. power supply connections pin name number i/o description v dd 7, 22 i positive digital voltage supply. gnd 8, 14, 21, 27 i digital ground. pins 14 and 27 need not be decoupled. note 1 the beginning of valid data will be delayed by one bclk_o if msbdel _o is selected (hl).
ad1890/AD1891 rev. 0 C7C theory of operation there are at least two logically equivalent methods of explaining the concept of asynchronous sample rate conversion: the high speed interpolation/decimation model and the polyphase filter bank model. using the ad1890 and AD1891 sampleports does not require understanding either model. this section is included for those who wish a deeper understanding of their operation. interpolation/decimation model in the high speed interpolation/decimation model, illustrated in figure 1, the sampled data input signal (plot a in figure 1) is interpolated at some ratio (iratio) by inserting iratio-1 zero valued samples between each of the original input signal samples (plot b in figure 1). the frequency domain characteris- tics of the input signal are unaltered by this operation, except that the zero-padded sequence is considered to be sampled at a frequency which is the product of original sampling frequency multiplied by iratio. the zero-padded values are fed into a digital fir low-pass filter (plot c in figure 1) to smooth or integrate the sequence, and limit the bandwidth of the filter output to 20 khz. the interpo- lated output signal has been quantized to a much finer time scale than the original sequence. the interpolated sequence is then passed to a zero-order hold functional block (physically implemented as a register, plot d in figure 1) and then asyn- chronously resampled at the output sample frequency (plot e in figure 1). this resampling can be thought of as a decimation operation since only a very few samples out of the great many interpolated samples are retained. the output values represent the nearest values, in a temporal sense, produced by the inter- polation operation. there is always some error in the output sample amplitude due to the fact that the output sampling switch does not close at a time that exactly corresponds to a point on the fine time scale of the interpolated sequence. how- ever, this error can be made arbitrarily small by using a very large interpolation ratio. the ad1890/AD1891 sampleport asrcs use an equivalent iratio of 65,536 to provide 16-bit accuracy ( ? C96 db thd+n) across the 0 to 20 khz audio band. the number of fir filter taps and associated coefficients is approximately 4 million. the equivalent fir filter convolution frequency (or upsample frequency) is 3.2768 ghz, and the fine time scale has resolution of about 300 ps. various propri- etary efficiencies are exploited in the ad1890/AD1891 asrcs to reduce the complexity and throughput requirements of the hardware implied by this interpolation/decimation model. input signal output signal zero stuff interpolation fir low pass filter zero order hold register resampling decimation a bc de b c d e a time amp figure 1. interpolation/decimation modeltime domain view
ad1890/AD1891 C8C rev. 0 polyphase filter bank model although less intuitively understandable than the interpolation/ decimation model, the polyphase filter bank model is useful to explore because it more accurately portrays the operation of the actual ad1890/AD1891 sampleport hardware. in the polyphase filter bank model, the stored fir filter coefficients are thought of as the impulse response of a highly oversampled 0 to 20 khz low-pass prototype filter, as shown in figure 2. if this low-pass filter is oversampled by a factor of n, then it can be conceptu- ally decomposed into n different subfilters, each filter consist- ing of a different subset of the original set of impulse response samples. if the temporal position of each of the subfilters is maintained, then they can be summed to recreate the original oversampled impulse response. since the original impulse response is highly oversampled, the more sparsely sampled subfilters still individually meet the nyquist criterion (i.e., they are adequately sampled). the baseband magnitude and phase responses of the subfilters are identical. the out-of-band (i.e., alias) regions of the subfilters however have phase responses which are shifted relative to one another, in a manner that causes them to cancel when they are summed. the subfilter coefficients are then aligned to the left, as shown in figure 3, so that the first coefficient of each subfilter is aligned to the first point on a coarse time scale. (this concep- tual step accounts for how the hardware implementation is able to operate at the slower rate corresponding to the coarse time scale.) each subfilter has been shifted in time by a different amount, and though they still share identical magnitude responses, they now have in-band phase responses which have fractionally different slopes (i.e., group delays). amp time oversampled low pass filter impulse response decomposed into four subfilters phase 0 deg 90 180 270 1/4fs 1/2fs 3/4fs fs freq amp 1/4fs 1/2fs 3/4fs fs 1/4fs 1/2fs 3/4fs fs 1/4fs 1/2fs 3/4fs fs 1/4fs 1/2fs 3/4fs fs figure 2. four polyphase subfilters in the time and frequency domains
ad1890/AD1891 rev. 0 C9C amp time subfilter coefficients aligned to the left t sin = 1/f sin freq f sin /2 f sin /2 f sin /2 f sin /2 f sin /2 phase delay = nominal delay = nominal delay = nominal ?.25/f sin delay = nominal ?.5/f sin delay = nominal ?.75/f sin figure 3. four polyphase subfilters realigned to coarse time grid polyphase filter 1 polyphase filter 2 polyphase filter 3 polyphase filter 4 polyphase filter 5 polyphase filter 6 polyphase filter 7 input signal polyphase filter n-1 polyphase filter n select n to 1 mux output signal sample clock tracking circuit parallel polyphase filter bank figure 4. polyphase filter bank modelconceptual block diagram the full set of subfilters can be considered to form a parallel bank of polyphase filters which have decrementing, linear phase group delays. all of the polyphase filters conceptually pro- cess the input signal simultaneously, as illustrated in figure 4, at the input sample rate.
ad1890/AD1891 C10C rev. 0 fifo write address generator fifo serial data input unit fifo read address generator accumulator serial data output unit sample clock ratio servo control loop polyphase coefficient rom rom address generator polyphase filter selector data_i lr_i lr_o wclk_o bclk_o lr_i wclk_i bclk_i fir convolver data_o start address frequency response compression f sout < f sin lr_i lr_o lr_i (f sin ) lr_o (f sout ) figure 6. ad1890/AD1891 functional block diagram asynchronous sample rate conversion under the polyphase filter bank model is accomplished by selecting the output of a particu- lar polyphase filter on the basis of the temporal relationship be- tween the input sample clock and the output sample clock events. figure 5 shows the desired filter group delay as a func- tion of the relative time difference between the current output sample clock and the last input sample clock. if an output sample is requested late in the input sample period, then a short filter delay is required, and if an output sample is requested early in the input sample period, then a long filter delay is re- quired. this nonintuitive result arises from the fact that fir fil- ters always produce some delay, so that selecting a filter with shorter delay moves the interpolated sample closer to the newest input sample. a short delay corresponds to a large offset into the dense fir filter coefficient array, and a long delay corresponds to a small offset. note that because the output sample clock can arrive at any arbitrary time with respect to the input sample clock, the selection of a polyphase filter with which to convolve the input sequence occurs on every output sample clock event. occasion- ally the fifo which holds the input sequence in the fir con- volver is either not incremented, or incremented by two between output sample clocks (see periods a and b in figure 5); this happens more often when the input and output sample clock frequencies are dissimilar than when they are close together. however, in this situation, an appropriate polyphase filter is selected to process the input signal, and thus an accurate output sample is computed. input and output samples are not skipped or repeated (unless the input fifo underflows or overflows), as is the case in some other sample rate converter implementations. to obtain an accurate conversion, a large number of polyphase filters are needed. the ad1890/AD1891 sampleports use the equivalent of 65,536 polyphase filters to achieve their profes- sional audio quality distortion and dynamic range specifications. sample clock tracking it should be clear that, in either model, the correct computation of the ratio between the input sample rate (as determined from the left/ right input clock, l r _i) and the output sample rate (as determined from the left/ right output clock, l r _o) is critical to the quality of the output data stream. it is straightforward to compute this ratio if the sample rates are fixed and synchronous; the challenge is to accurately track dynamically varying and asynchronous sample rates, as well as to account for jitter. ab output sequence past future amplitude amplitude short delay long delay small offset large offset required filter group delay to compute requested output sample offset into dense fir filter coefficient array to access required polyphase filter input sequence figure 5. input and output clock event relationship the ad1890/AD1891 sampleports solve this problem by embedding the ratio computation circuit within a digital servo control loop, as shown in figure 6. this control loop includes special provisions, to allow for the accurate tracking of dynami- cally changing sample rates. the outputs of the control loop are the starting read addresses for the input data fifo and the filter coefficient rom. these start addresses are used by the fifo and rom address generators, as shown in figure 6. the input data fifo write address is generated by a counter which is clocked by the input sample clock (i.e., l r _i). it is very important that the fifo read address and the fifo write ad- dress do not cross, as this means that the fifo has either underflowed or overflowed. this consideration affects the choice of settling time of the control loop. when a step change in the sample rate occurs, the relative positions of the read and write addresses will change while the loop is settling. a fast set- tling loop will act to keep the fifo read and write addresses separated better than a slow settling loop. the ad1890/ AD1891 include a user selectable pin (setlslw) to set the loop settling time that essentially changes the coefficients of the digital servo control loop filter. the state of the setlslw pin can be changed on-the-fly but is normally set and forgotten.
ad1890/AD1891 rev. 0 C11C sample clock jitter rejection the loop filter settling time also affects the ability of the ad1890/AD1891 asrcs to reject sample clock jitter, since the control loop effectively computes a time weighted average or estimated new output of many past input and output clock events. this first order low pass filtering of the sample clock ratio provide the ad1890/AD1891 with their jitter rejection characteristic. in the slow settling mode, the ad1890/AD1891 attenuate jitter frequencies higher than 3 hz ( ? 800 ms for the control loop to settle to an 18-bit pure sine wave), and thus reject all but the most severe sample clock jitter; performance is essentially limited only by the fir filter. in the fast settling mode, the asrcs attenuate jitter components above 12 hz ( ? 200 ms for the control loop to settle). due to the effects of on-chip synchronization of the sample clocks to the 16 mhz (62.5 ns) mclk master clock, sample clock jitter must be a large percentage of the mclk period (>10 ns) before perfor- mance degrades in either the slow or fast settling modes. note that since both past input and past output clocks are used to compute the filtered current internal output clock request, jit- ter on both the input sample clock and the output sample clock is rejected equally. in summary: the fast settling mode is best for applications when the sample rates will be dynamically altered (e.g., varispeed situations) while the slow settling mode provides the most sample clock jitter rejection. clock jitter can be modeled as a frequency modulation process. figure 7 shows one such model, where a noise source combined with a sine wave source modulates the carrier frequency gen- erated by a voltage controlled oscillator. noise source vco digital out analog in adc voltage source s noise waveform sine wave figure 7. clock jitter modeled as a modulated vco if the jittered output of the vco is used to clock an analog-to- digital converter, the digital output of the adc will be contami- nated by the presence of jitter. if the noise source is spectrally flat (i.e., white jitter), then an fft of the adc digital output would show a spectrum with a uniform noise floor which is el- evated compared to the spectrum with the noise source turned off. if the noise source has distinct frequency components (i.e., correlated jitter), then an fft of the adc digital output would show symmetrical sidebands around the adc input sig- nal, at amplitudes and frequencies determined by frequency modulation theory. one notable result is that the level of the noise or the sidebands is proportional to the slope of the input signal, i.e., the worst case occurs at the highest frequency full- scale input (a full-scale 20 khz sinusoid). the ad1890/AD1891 apply rejection to these jitter frequency components referenced to the input signal. in other words, if a 5 khz digital sinusoid is applied to the asrc, depending on the settling mode selected, the asrc will attenuate sample clock jitter at either 3 hz above and below 5 khz (slow settling) or 12 hz above and below 5 khz (fast settling). the rolloff is 6 db per octave. as an example, suppose there was correlated jitter present on the input sample clock with a 1 khz component, associated with the same 5 khz sinusoidal input data. this would produce sidebands at 4 khz and 6 khz, 3 khz and 7 khz, etc., with amplitudes that decrease as they move away from the input signal frequency. for the slow settling mode case, 1 khz represents more than nine octaves (relative to 3 hz), so the first two sideband pairs would be attenuated by more than 54 db. for the fast settling mode case, 1 khz repre- sents more than seven octaves (relative to 12 hz), so that the first two sideband pairs would be attenuated by more than 42 db. the second and higher sideband pairs are attenuated even more because they are spaced further from the input signal frequency. group delay modes the other parameter that determines the likelihood of fifo in- put overflow or output underflow is the fifo depth. this is the parameter that is selected by the gpdlys pin (ad1890 only; this pin is a no connect for the AD1891). the drawback with increasing the fifo depth is increasing the devices overall group delay, but most applications are insensitive to a small in- crease in group delay. [this fifo-induced group delay is better termed transport delay, since it is frequency independent, and should be kept conceptually distinct from the notion of group delay as used in the polyphase filter bank model. the total group delay of the ad1890/AD1891 equals the fifo transport delay plus the fir (polyphase) filter group delay.] in the short group delay mode, the fifo read and write point- ers are separated by five memory locations ( ? 100 m s equivalent transport delay at a 50 khz sample rate). this is added to the fir filter delay (64 taps divided by 2) for a total nominal group delay in short mode of ? 700 m s. the short group delay mode is useful when the input and output sample clocks are asynchro- nous but either do not vary or change very slowly. in the long group delay mode (ad1890 only, the AD1891 is always in the short group delay mode), the fifo read and write pointers are separated by 96 memory locations ( ? 2 ms equiva- lent transport delay). this is added to the fir filter delay (64 taps divided by 2) for a total nominal group delay in long mode of ? 3 ms. the long group delay mode is useful when the input and output sample clocks are asynchronous and changing relative to one another, such as during varispeed effects. these delays are deterministic and constant except when f sout drops below f sin which causes the number of fir filter taps to increase (see cutoff frequency modification below). in either mode, if the fifo read and write addresses cross, the mute_o signal will be asserted. note that in all modes and under all con- ditions, both the highly oversampled low-pass prototype and the polyphase subfilters of the ad1890/AD1891 asrcs possess a linear phase response. the ad1890 has been designed so that when it is in long group delay mode and fast settling mode, a full 2:1 step change (i.e., occurring between two samples) in sample frequency ratio can be tolerated without output mute.
ad1890/AD1891 C12C rev. 0 cutoff frequency modification the final important operating concept of the asrcs is the mod- ification of the filter cutoff frequency when the output sample rate (f sout ) drops below the input sample rate (f sin ), i.e., during downsampling operation. the ad1890/AD1891 auto- matically reduces the polyphase filter cutoff frequency under this condition. this lowering of the cutoff frequency (i.e., the reduction of the input signal bandwidth) is required to avoid alias distortion. the ad1890/AD1891 soundports take advan- tage of the scaling property of the fourier transform which can be stated as follows: if the fourier transform of f(t) is f(w), then the fourier transform of f(k t) is f(w/k). this property can be used to linearly compress the frequency response of the filter, simply by multiplying the coefficient rom addresses (shown in figure 6) by the ratio of f sout to f sin whenever f sout is less than f sin . this scaling property works without spectral distor- tion because the time scale of the interpolated signal is so dense (300 ps resolution) with respect to the cutoff frequency that the discrete-time representation is a close approximation to the con- tinuous time function. the cutoff frequency (C3 db down) of the fir filter during downsampling is given by the following relation: downsampling cutoff frequency = (f sout /44.1 khz) 20 khz the ad1890/AD1891 frequency response compression circuit includes a first order low-pass filter to smooth the filter cutoff frequency selection during dynamic sample rate conditions. this allows the asrc to avoid objectionable clicking sounds that would otherwise be imposed on the output while the loop settles to a new sample rate ratio. hysteresis is also applied to the filter selection with approximately 300 hz of cutoff fre- quency noise margin, which limits the available selection of cutoff frequencies to those falling on an approximately 300 hz frequency grid. thus if a particular sample frequency ratio was reached by sliding the output sample frequency up, it is possible that a filter will be chosen with a cutoff frequency that could dif- fer by as much as 300 hz from the filter chosen when the same sample frequency ratio was reached by sliding the output sample frequency down. this is necessary to ensure that the filter selec- tion is stable even with severely jittered input sample clocks. note that when the filter cutoff frequency is reduced, the transi- tion band of the filter becomes narrower since the scaling prop- erty affects all filter characteristics. the number of fir filter taps necessarily increases because there are now a smaller num- ber of longer length polyphase filters. nominally, when f sout is greater than f sin , the number of taps is 64. when f sout is less than f sin, the number of taps linearly increase to a maximum of 128 when the ratio of f sout , to f sin equals 1:2. the number of filter taps as a function of sample clock ratio is illustrated in fig- ure 8. the natural consequence of this increase in filter taps is an increase in group delay. when the ad1890/AD1891 output sample frequency is higher than the input sample frequency (i.e., upsampling operation), the cutoff frequency of the fir polyphase filter can be greater than 20 khz. the cutoff frequency of the fir filter during upsampling is given by the following relation: upsampling cutoff frequency = (f sin /44.1 khz) 20 khz noise and distortion phenomena there are three noise/distortion phenomena that limit the per- formance of the ad1890/AD1891 asrcs. first, there is 0.5 1.0 1.5 2.0 number of filter taps 128 64 f sout /f sin upsampling down- sampling figure 8. number of filter taps as a function of f sout /f sln broadband, gaussian noise which results from polyphase filter selection quantization. even though the ad1890/AD1891 have a large number of polyphase filters (the equivalent of 65,536) to choose from, the selection is not infinite. second, there is narrow-band noise which results from the non-ideal synchroni- zation of the sample clocks to the system clock mclk, which leads to a non-ideal computation of the sample clock ratio, which leads to a non-ideal polyphase filter selection. this noise source is narrowband because the digital servo control loop averages the polyphase filter selection, leading to a strong corre- lation between selections from output to output. in slow mode, the selection of polyphase filters is completely unaffected by the clock synchronization. in fast mode, some narrowband noise modulation may be observed with very long fft measure- ments. this situation is analogous to the behavior of a phase locked loop when presented with a noisy or jittered input. third, there are distortion components that are due to the non-infinite stopband rejection of the low-pass filter response. non-infinite stopband rejection means that some amount of out-of-band spectral energy will alias into the baseband. the ad1890/AD1891 performance specifications include the effects of these phenomena. note that figures 15 through 17 are shown with full-scale input signals. the distortion and noise components will scale with the input signal amplitude. in other words, if the input signal is at- tenuated by C20 db, the distortion and noise components will also be attenuated by C20 db. this dependency holds until the effects of the 20-bit input quantization are reached.
ad1890/AD1891 rev. 0 C13C appearance of the msb of data is synchronous with the rising edge of the left/ right clock for the left channel and the falling edge of left/ right clock for the right channel. the msb is delayed by one bit clock after the left/ right clock if the msb delay mode is selected. the word clock is not required in the left/ right clock triggered mode, and should be tied either hi or lo. figure 23 shows the bit clock in the optional gated or burst mode; the bit clock is inactive between data fields, and can take either the hi state or the lo state while inactive. note that there is no requirement for a delay between the left channel data and the right channel data. the left/ right clocks and the word clocks can transition immediately after the lsb of the data, so that the msb of the subsequent channel appears without any timing delay. the AD1891 is therefore capable of a 32-bit frame mode, in which both 16-bit channels are packed into a 32-bit clock period. more generally, there is no particular requirement for when the left/ right clock falls (i.e., there is no left/ right clock duty cycle or pulse width specification), provided that the left/ right clock frequency equals the intended sample frequency, and there are sufficient bit clock periods to clock in or out the intended number of data bits. control signals the gpdlys, setlslw, bkpol_i, bkpol_o, trglr_i, trglr_o, msbdly_i, and msbdly_o inputs are asyn- chronous signals in that they need obey no particular timing relation to mclk or the sample clocks. ordinarily, these pins are hardwired or connected to an i/o register for microprocessor control. the only timing requirement on these pins is that the control signals are stable and valid before the first serial input data bit (i.e., the msb) is presented to the ad1890/AD1891. reset figure 25 shows the reset timing for the ad1890/AD1891 sampleports. mclk must be running when reset is asserted, and the bit clocks, the word clocks and the left/ right clocks may also be running. when the ad1890/AD1891 come out of reset, they default to a f sin to f sout ratio of 1:1. the fil- ter pipeline is not cleared. however, the mute output goes hi for at least 128 cycles, adequate to allow the pipeline to clear. if f sin differs significantly from f sout , then the ad1890/AD1891 sample clock servo control loop also has to settle. while settling, the mute output will be hi. after the external system resets the ad1890/AD1891, it should wait until the mute output goes lo before clocking in serial data. there is no requirement for using the reset pin at power-up or when the input or output sample rate changes. if it is not used, the ad1890/AD1891 will settle to the sample clocks sup- plied within ? 200 ms in fast-settling mode or within ? 800 ms in slow-settling mode. operating features serial input/output ports the ad1890/AD1891 use the frequency of the left/ right input clock (l r _i) and the left/ right output clock (l r _o) signals to determine the sample rate ratio, and therefore these signals must run continuously and transition twice per sample period. (the l r _i clock frequency is equivalent to f sin and the l r _o clock frequency is equivalent to f sout .) the other clocks (wclk_i, wclk_o, bclk_i, bclk_o) are edge sensitive and may be used in a gated or burst mode (i.e., a stream of pulses during data transmission or reception followed by periods of inactivity). the word clocks and bit clocks are used only to write data into or read data out of the serial ports; only the left/ right clocks are used in the internal dsp blocks. it is important that the left/ right clocks are clean with monotonic rising and falling edge transitions and no excessive overshoot or undershoot which could cause false triggering on the ad1890/AD1891. the ad1890/AD1891s flexible serial input and output ports consume and produce data in twos-complement, msb-first format. the left channel data field always precedes the right channel data field; the current channel being consumed or pro- duced is indicated by the state of the left/ right clock (l r _i and l r _o). a left channel field, right channel field pair is called a frame. the input data field consists of 4 to 20 bits for the ad1890, and 4 to 16 bits for the AD1891. the output data field consists of 4 to 24 bits for both devices. the input signals are specified to ttl logic levels, and the outputs swing to full cmos logic levels. the ports are configured by pin selections. serial i/o port modes the ad1890/AD1891 has pin-selectable bit clock polarity for the input and output ports. in normal mode (bkpol_i or bkpol_o lo) the data is valid on the rising edge. in the inverted mode (bkpol_i or bkpol_o hi) the data is valid on the falling edge. both modes are shown in figures 22 and 23. in the pin selectable msb delay mode, which can be set inde- pendently for the input and output ports, the msb is delayed by one bit clock. this is useful for i 2 s format compatibility and for ease of interfacing to some dsp processors. both the msb de- lay mode (msbdly_i or msbdly_o hi) and the msb non-delay mode (msbdly_i or msbdly_o lo) are shown in figures 22 and 23. the ad1890/AD1891 sampleport serial ports operate in either the word clock (wclk_i, wclk_o) triggered mode or left/ right clock (l r _i, l r _o) triggered mode. these modes can be utilized independently for the input and output ports, by reset- ting or setting the trglr_i and trglr_o control lines respectively. in the word clock triggered mode, as shown in fig- ure 22, after the left/ right clock is valid, the appearance of the msb of data is synchronous with the rising edge of the word clock (or delayed by one bit clock if the msb delay mode is selected). note that the word clock is rising edge sensitive, and can fall anytime after it is sampled hi by the bit clock. in the left/ right clock triggered mode, as shown in figure 23, the
ad1890/AD1891 C14C rev. 0 80 0 80 24 8 8 16 0 48 32 40 56 64 72 72 64 56 48 40 32 24 16 f sin ?khz f sout ?khz 70khz f sin /f sout = 2/1 f sin /f sout = 1/1 f sin /f sout = 1/2 10khz 70khz upsampling downsampling figure 9. allowable input and output sample frequencies mclk = 20 mhz case 80 0 80 24 8 8 16 0 48 32 40 56 64 72 72 64 56 48 40 32 24 16 f sin ?khz f sout ?khz 56khz f sin /f sout = 2/1 f sin /f sout = 1/1 f sin /f sout = 1/2 8khz 56khz downsampling upsampling figure 10. allowable input and output sample frequencies mclk = 16 mhz case 80 0 80 24 8 8 16 0 48 32 40 56 64 72 72 64 56 48 40 32 24 16 f sin ?khz f sout ?khz 42khz f sin /f sout = 2/1 f sin /f sout = 1/1 f sin /f sout = 1/2 6khz 42khz up- sampling down- sampling figure 11. allowable input and output sample frequencies mclk = 12 mhz case application issues dither due to the large output word length, no redithering of the ad1890/AD1891 output is necessary. this assumes that the input is properly dithered and the user retains the same or greater number of output bits as there are input bits. the ad1890/AD1891 output bit stream may thus be used directly as the input to downstream digital audio processors, storage media or output devices. if the ad1890/AD1891 is to be used to dramatically down- sample (i.e., output sample frequency is much lower than input sample frequency), the input should be sufficiently dithered to account for the limiting of the input signal bandwidth (which reduces the rms level of the input dither). no dither is inter- nally used or applied to the audio data in the ad1890/AD1891 sampleports. decoupling and pcb layout the ad1890/AD1891 asrcs have two power (pins 7 and 22) and two ground (pins 8 and 21) connections to minimize output switching noise and ground bounce. [pins 14 and 27 are actu- ally control inputs, and should be tied lo, but need not be decoupled.] the dip version places these pins at the center of the device to optimize switching performance. the ad1890/ AD1891 should be decoupled with two high quality 0.1 m f or 0.01 m f ceramic capacitors (preferably surface mount chip capacitors, due to their low inductance), one between each v dd / gnd pair. best practice pcb layout and interconnect guide- lines should be followed. this may include terminating mclk or the bit clocks if excessive overshoot or undershoot is evident and avoiding parallel pcb traces to minimize digital crosstalk between clocks and control lines. note that dip and plcc sockets reduce electrical performance due to the additional in- ductance they impose; sockets should therefore be used only when required. master clock using a 16 mhz mclk, the nominal range of sample frequen- cies that the ad1890/AD1891 accept is from 8 khz to 56 khz. other sample frequency ranges are possible by linearly scaling the mclk frequency. for example, a 12 mhz mclk would yield a sample frequency range of 6 khz to 42 khz, and a 20 mhz mclk would yield a sample frequency range of 10 khz to 70 khz. the approximate relative upper bound sample frequency is the mclk frequency divided by 286; the approximate relative lower bound sample frequency is the mclk frequency divided by 2000. the audio performance will not degrade if the sample frequencies are kept within these bounds. the ad1890/AD1891 sampleports are production tested with a 20 mhz mclk. note that due to mclk-driven finite register length constraints, there is a minimum input sample frequency (l r _i). the allowable input and output sample frequency ranges for mclk frequencies of 20 mhz, 16 mhz and 12 mhz are shown in figures 9, 10 and 11.
ad1890/AD1891 rev. 0 C15C multiple asrc synchronization and performance degradation multiple parallel ad1890/AD1891 asrcs may be used in a single system. multiple ad1890/AD1891s can be synchro- nized by simply sharing the same reset and mclk lines, and ensuring that all the asrcs leave the reset state on the same mclk falling edge. no other provision is necessary since the different ad1890/AD1891s will process samples identically if they are presented with the same input and output clocks (neglecting the effect of excessive clock skew on the pcb, as well process variations between asrcs which could cause dif- ferent devices to trigger at slightly different times on excessively slow rising or falling clock edges). it is also likely that several ad1890/AD1891s could end up in a serial cascade arrangement, either in a single systems design or as the result of two or more systems, each using a single ad1890/ AD1891 in the signal path. the audio signal quality will be degraded with each pass through an asrc, though to a very minor degree. the thd+n performance will degrade by 3 db with every doubling of the number of passes through an asrc. for example, the ad1890 thd+n specification of C106 db (at 1 khz) will rise to C103 db if the signal makes two passes through an asrc. the overall system thd+n specification will rise to C100 db with four passes, and so on. clipping under certain rare input conditions, it is possible for the ad1890/AD1891 asrc to produce a clipped output sample. this situation is best comprehended by employing the interpola- tion/decimation model. if two consecutive samples happened to have full-scale amplitudes (representing the peak of a full-scale sine wave, for example), the interpolated sample (or samples) between these two samples might have an amplitude greater than full scale. as this is not possible, the ad1890/AD1891 will compute a full-scale amplitude for the interpolated sample or samples (see figure 12). clipping can also arise due to the pre-echo and post-echo gibbs phenomena of the fir filter, when presented with a full-scale step input. the result of this erroneous or clipped output sample may be measured as an extremely small decrease in headroom for transient signals. correctly interpolated sample clipped interpolated sample full scale amplitude time figure 12. clipped output sample varispeed it is also envisioned that the ad1890 will be used in varispeed applications. the ad1890 and AD1891 sampleports are very useful for converting an input data stream with a variable sample rate (and therefore pitch characteristic) into an output data stream with a constant sample rate. options for sample rate conversion over a wider range there are systems which require sample rate conversion over a range which is wider than the 1:2 or 2:1 range provided by a single ad1890 or AD1891, such as for scrubbing in digital audio editors. there are at least two options in this situation. the first is to use a programmable dsp chip to perform simple integer ratio interpolation or decimation, and then use the ad1890/AD1891 when this intermediate output sample fre- quency is within the 1:2 or 2:1 range of the final desired output sample frequency. the second is to use multiple ad1890/ AD1891 devices cascaded in series to achieve the required sample rate range. almost synchronous operation it is possible to apply input and output sample frequencies which are very close (within a few hz) or in fact synchronous (l r _i and l r _o tied together). there is no performance pen- alty when using the ad1890/AD1891 in almost synchronous applications. indeed, there is a very slight performance benefit when the input and output sample clocks are synchronous since the alias distortion components which arise from the non-infinite stopband attenuation of the fir filter will pile up exactly on top of the sinusoidal frequency components of the input signal, and will thus be masked. system mute the mute function applies to both right and left channels on the ad1890/AD1891. the user can include a system specific out- put mute signal, while retaining the automatic mute feature of the ad1890/AD1891 by using the circuit shown in figure 13. ad1890/AD1891 external system mute active hi 15 16 mute_o mute_i figure 13. external mute circuit
ad1890/AD1891 C16C rev. 0 performance graphs 100 20k 10k 1k 20 frequency ?hz ?0.00 ?0.00 ?0.00 ?0.00 ?10.0 ?00.0 ?30.0 ?20.0 ?40.0 ?60.0 ?50.0 dbfs figure 14a. ad1890dynamic range from 20 hz to 20 khz, C60 dbfs, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window dbfs 0.0 ?0.00 ?40.00 ?0.00 ?0.00 ?0.00 ?20.00 ?00.00 20 100 20k 10k 1k frequency ?hz figure 15a. ad18901 khz tone at 0 dbfs, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window dbfs 0.0 ?0.00 ?40.00 ?0.00 ?0.00 ?0.00 ?20.00 ?00.00 20 100 20k 10k 1k frequency ?hz dbfs 0.0 ?0.00 ?40.00 ?0.00 ?0.00 ?0.00 ?20.00 ?00.00 20 100 20k 10k 1k frequency ?hz figure 16a. ad189015 khz tone at 0 dbfs, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window 100 20k 10k 1k 20 frequency ?hz ?0.00 ?0.00 ?0.00 ?0.00 ?10.0 ?00.0 ?30.0 ?20.0 ?40.0 ?60.0 ?50.0 dbfs figure 14b. AD1891dynamic range from 20 hz to 20 khz, C60 dbfs, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window dbfs 0.0 ?0.00 ?40.00 ?0.00 ?0.00 ?0.00 ?20.00 ?00.00 20 100 20k 10k 1k frequency ?hz figure 15b. AD18911 khz tone at 0 dbfs, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window dbfs 0.0 ?0.00 ?40.00 ?0.00 ?0.00 ?0.00 ?20.00 ?00.00 20 100 20k 10k 1k frequency ?hz figure 16b. AD189115 khz tone at 0 dbfs, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window
ad1890/AD1891 rev. 0 C17C ?0.00 ?00.0 ?20.0 ?10.0 ?0.00 ?5.00 ?05.0 ?15.0 ?5.00 dbfs 100 20k 10k 1k 20 frequency ?hz figure 17a. ad1890thd+n vs. frequency, 48 khz input sample frequency, 44.1 khz output sample frequency, full-scale input signal ?0.00 ?10.0 ?30.0 ?20.0 ?00.0 ?05.0 ?15.0 ?25.0 ?5.00 0.0 ?0.0 ?00 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 20khz 1khz amplitude ? dbfs dbfs figure 18a. ad1890thd+n vs. input amplitude, 44.1 khz input sample frequency, 48 khz output sample frequency, 1 khz and 20 khz tones 100 20k 10k 1k 20 frequency ?hz ?20.0 ?0.00 ?00.0 ?10.0 ?0.00 ?5.00 ?05.0 ?15.0 ?5.00 dbfs figure 17b. AD1891thd+n vs. frequency, 48 khz input sample frequency, 44.1 khz output sample frequency, full-scale input signal 0.0 ?0.0 ?00 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 ?0.0 1khz amplitude ? dbfs dbfs ?6.00 ?00.00 ?8.00 ?4.00 ?5.00 ?7.00 ?9.00 ?2.00 ?3.00 ?0.00 ?1.00 20khz figure 18b. AD1891thd+n vs. input amplitude, 44.1 khz input sample frequency, 48 khz output sample frequency, 1 khz and 20 khz tones 10.000 8.0000 6.0000 4.0000 2.0000 0.0 ?.000 ?.000 ?.000 ?.000 ?0.00 dbfs 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 frequency ?hz 44.1k 40k 35k 30k 25k figure 19. ad1890/AD1891 digital filter signal transfer function, 10 khz to 20 khz, 44.1 khz input sample frequency, 44.1, 40, 35, 30 and 25 khz output sample frequencies
ad1890/AD1891 C18C rev. 0 0.0 ?40.0 ?0.00 ?20.0 ?00.0 ?0.00 ?0.00 ?0.00 dbfs 20k 2k 20 18k 16k 14k 12k 10k 8k 6k 4k frequency ?hz figure 20a. ad1890twintone, 10 khz and 11 khz, 44.1 khz input sample frequency, 48 khz output sample frequency, 16k-point fft, bh4 window 0.0 ?40.0 ?0.00 ?20.0 ?00.0 ?0.00 ?0.00 ?0.00 dbfs 20k 18k 16k 14k 12k 10k 8k 6k frequency ?hz 2k 20 4k figure 20b. AD1891twintone, 10 khz and 11 khz, 44.1 khz input sample frequency, 48 khz output sample frequency, 16k-point fft, bh4 window 0.0 ?40.0 10k ?0.00 ?20.0 1k ?00.0 20 ?0.00 ?0.00 ?0.00 9k 8k 7k 6k 5k 4k 3k 2k dbfs frequency ?hz figure 21. ad1890/AD18915 khz tone at 0 dbfs with 100 ns p-p binomial jitter on l/ r clocks, fast settling mode, 48 khz input sample frequency, 44.1 khz output sample frequency, 16k-point fft, bh4 window data in/out no msb delay mode bclk_i, bclk_o normal mode bclk_i, bclk_o inverted mode lr_i, lr_o input wclk_i, wclk_o input input data in/out msb delay mode msb msb? msb? left data msb lsb lsb+1 lsb+2 msb-1 msb-2 right data lsb+1 lsb msb msb? msb? msb? left data right data lsb+1 lsb msb-3 msb msb-1 msb-2 lsb figure 22. ad1890/AD1891 serial data input and output timing, word clock triggered mode
ad1890/AD1891 rev. 0 C19C bclk_i, bclk_o normal mode bclk_i, bclk_o inverted mode input data in/out no msb delay mode msb? msb? left data msb msb-1 right data lsb+1 lsb msb-3 msb msb-1 msb-2 lsb data in/out msb delay mode msb msb? msb? left data msb lsb lsb+1 lsb+2 msb-1 msb-2 right data lsb+1 lsb lr_i, lr_o input figure 23. ad1890/AD1891 serial data input and output timing, left/ right clock triggered mode mclk t rs t rpwl reset figure 25. ad1890/AD1891 reset timing mclk t mclk t mpwl t mpwh figure 24. ad1890/AD1891 mclk timing t dh bclk_i, bclk_o normal mode bclk_i, bclk_o inverted mode wclk_i wclk_o t bpwh msb msb-1 data in no msb delay mode data out no msb delay mode data in msb delay mode data out msb delay mode t doh msb msb msb-1 t bpwl t bpwl t bpwh t lrso t ds t lrsi t wso t wsi t dh t dpd msb-1 msb t ds t doh msb-1 t dpd lr_i lr_o figure 26. ad1890/AD1891 bit clock, word clock, left/ right clock and data timing
ad1890/AD1891 C20C rev. 0 outline dimensions dimensions shown in inches and (mm). c1820C18C7/93 printed in u.s.a. n-28 28-lead plastic dip 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc pin 1 0.580 (14.73) 0.485 (12.32) 0.200 (5.05) 0.125 (3.18) 0.070 (1.77) max seating plane 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 1.565 (39.70) 1.380 (35.10) 1 14 15 28 0.625 (15.87) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) p-28a 28-lead plcc 4 pin 1 identifier 5 26 25 11 12 19 18 top view (pins down) 0.495 (12.57) 0.485 (12.32) sq 0.456 (11.58) 0.450 (11.43) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16)

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